1. Field of the Invention
The present invention relates generally to sigma-delta modulators. More particularly, the present invention relates to methods of cascading sigma-delta modulators.
2. Description of Related Art
Oversampled interpolative (or sigma-delta) modulators comprise at least one integration stage or filter followed by a quantization stage (most typically a comparator) and a feedback from the output of the quantization stage to the input of the integration stage. Depending upon the number of integration stages, sigma-delta modulators can be divided into order types, e.g., second-order, third-order, or fourth-order.
Sigma-delta modulators have come to be commonly used to perform analog-to-digital (A/D) and digital-to-analog (D/A) conversion in a number of applications. These applications include coder-decoders (codecs), integrated services digital network (ISDN) equipment, and audio equipment.
The use of higher order sigma-delta modulators has become desirable in many applications for several reasons. One reason is because the introduction of higher order modulators increases the number of integrations to be carried out, which results in a decrease in the noise level of the passband as the quantization noise is shifted to a higher frequency level. Another reason is because the use of higher order modulators keeps the oversampling ratio (i.e., the ratio of the modulator clock to the Nyquist rate) low, which is desirable under certain conditions.
A number of efforts have heretofore been undertaken to develop higher order sigma-delta modulators. Five such efforts, those undertaken by Matsuya et al., Ribner, Chao et al., Karema et al., and the inventor of the present invention, Cabler, are discussed immediately below.
Matsuya, et al., in "A 16-Bit Oversampling A-D Conversion Technology Using Triple-Integration Noise Shaping", IEEE Journal of Solid State Circuits, Vol. SC-22, No. 6, pp. 921-929, December, 1987, have presented a method of cascading three or more first-order modulators in order to provide higher order noise shaping. A block diagram of this circuit is shown in FIG. 1 in the related application incorporated herein. The technique employed in this circuit, well known to those skilled in the art as the "MASH" technique, is described at length in U.S. Pat. No. 5,061,928 to Karema. That discussion is incorporated herein by this reference thereto. Although the circuit in FIG. 1 in the related application could be discussed at length, given the level of skill of those skilled in the art, it suffices here to say that the circuit of that figure depicts three cascaded first-order modulators (each generally designated by reference numeral 2). Each first-order modulator 2 comprises an integrator 4 and a quantizer 6. The difference between the output signals of the integrators 4 and the quantizers 6 of the two topmost modulators 2 are fed to subsequent modulators 2. By doing this, quantized noise is moved up out of band, where it can be subsequently, and easily, filtered out. The MASH technique has a number of shortcomings however. First, the MASH technique requires tight matching of the characteristics of the modulators to achieve good resolution. The MASH technique also requires high op amp gains to accomplish the same results. Further, the technique has been shown to be quite sensitive to analog component mismatch when used as an A/D converter. Mismatches in the analog circuitry result in uncancelled quantization noise leaking into the passband. Theoretically, however, with regard to the circuit of FIG. 1 in the related application, if the input to the converter is given as x, and the quantization error of the last modulator is given as E.sub.3, the output, y, can be expressed as follows: EQU y=xz.sup.-3 +E.sub.3 (1-z.sup.-1).sup.3
As previously mentioned, Ribner also has worked to develop higher order sigma-delta modulators. Ribner, in "A Third-Order Multistage Sigma-Delta Modulator with Reduced Sensitivity to Nonidealities", IEEE J. Solid-State Circuits, Vol. 26, No. 12, pp, 1764-1774, December, 1991, and in U.S. Pat. Nos. 5,148,167, 5,148,166, and 5,065,157, has presented a method of cascading a second-order modulator with a first-order modulator. A block diagram of this circuit is shown in FIG. 2 in the related application wherein the second-order modulator is generally designated with reference numeral 8 and the first-order modulator generally designated with reference numeral 10. Referring to the bottommost portion of FIG. 2 in the related application, it is depicted that Ribner teaches combining the quantized outputs y.sub.1, y.sub.2 of the modulators 8,10 in such a manner that the quantization noise of the second-order section is cancelled while the quantization noise of the first-order section is shaped in a third-order manner. Once again, mathematically, if the input to the converter is given as x, and the quantization error of the first-order modulator is given as E.sub.2, the output, y, can be expressed as follows: EQU y=z.sup.-3 x+C(1-z.sup.-1).sup.3 E.sub.2
In this case a gain of 1/C was added between the modulators 8,10 in order to prevent the second modulator 10 from overflowing. In order to compensate for the factor of 1/C, a gain of C is added in the correction logic. This can be seen in FIG. 2 in the related application in the form of element 12 (the gain adding portion) and element 14 (the compensation portion).
Chao et al., in "A Higher Order Topology for Interpolative Modulators For Oversampling A/D Converters, IEEE Transactions on Circuits and Systems, Vol. 37, No. 3, pp. 309-318, March, 1990, have proposed a single loop structure for higher order sigma-delta modulators. These modulators consist of a multitude of integrators, feed-forward paths, feed-back paths, and a single quantizer in order to synthesize the desired noise shaping. These modulators suffer from the possibility that they may enter into a mode of self sustained oscillations for certain input values. Various methods have been proposed to desensitize these converters to this phenomena, all of which complicate the structure. It has been noted, however, that single stage first- and second-order modulators of this type do not suffer from this phenomena.
For audio applications, it is desired that the signal-to-total distortion, including noise, be equivalent to that of a standard 16-bit linear converter. Simulations have indicated that for an oversampling ratio of 64, and using practical circuit techniques, third-order modulators built based upon any of the above methods will exceed the performance of a standard 16-bit linear converter. However, the amount of margin beyond 16 bits is not very high. Therefore, it is desired that a sigma-delta converter be built with fourth-order noise shaping.
Karema et al., in U.S. Pat. No. 5,061,924, have introduced a fourth-order topology which comprises of a cascade of two second-order modulators. This is shown in FIG. 3 in the related application wherein the two second-order modulators are generally designated with reference numeral 16. As shown therein, a gain of 1/C (in the form of gain element 18) has been added between the two modulators in order to prevent overflow of the second modulator. As in Ribner's modulator depicted in FIG. 2 discussed alone, a digital circuit is added to Karema et al.'s cascade. This circuit, generally designated by reference numeral 20, is set forth at the bottom of FIG. 3 in the related application. This circuit combines the quantized outputs of the two second-order sections y.sub.1, y.sub.2 in such a manner that the quantization error of the first modulator is cancelled and the quantization error of the second modulator receives fourth-order shaping. Algebraically, if the input to the converter is given as x, and the quantization error of the second modulator is given as E.sub.2, then the output y can be expressed as: EQU y=z.sup.-4 x+C(1-z.sup.-1).sup.4 E.sub.2
In pending U.S. patent application Ser. No. 08/112,610, the inventor of the present invention teaches a system and method for cascading three sigma-delta modulators. Cabler's system and method involves applying an error signal representing the quantization error of a preceding modulator to a subsequent modulator. The error signal is scaled by a factor before being applied to a subsequent modulator. The quantized error signal of the subsequent modulator is then scaled by the reciprocal of the original scaling factor before being combined with the quantized outputs of the previous modulators. Combining the quantized outputs of the three modulators is performed so as to cancel the quantization error of the previous stages while shaping the noise at the last stage so that most of the noise is placed at high frequencies.
Thus, in Cabler's design, the quantization noise of each stage is obtained by taking the difference between the output and the input of the quantizer of each stage. This quantization noise is then fed to the subsequent stage. A correction network then removes the quantization noise from each of the previous stages in such a manner that the output is simply a delayed version of the input, plus a scaled version of the quantization noise from the last stage which has been shaped with a fourth-order high pass function.
Based upon the foregoing, it should be understood and appreciated that fourth-order sigma-delta modulators have important advantages over lesser order modulators in certain applications. Further on this point, the signal-to-noise ratio (SNR) of ideal sigma-delta modulators is given by the following equation: EQU SNR=(2L+1) 10 log (OSR)-10 log (.pi..sup.2L /2L+1)
where OSR is the oversampling ratio and L is the order of the modulator. For example, if L=3 and the OSR=64, the SNR equals 105 dB. If L=4 and OSR=64, the SNR equals 132.3 dB. Thus, a fourth-order loop has more inherent margin for 16-bit performance than does a third-order loop with the same oversampling ratio. Although fourth-order sigma-delta modulators, such as that taught by Karema et al., have heretofore been proposed, it is a shortcoming and deficiency of the prior art that there are not additional types of such modulators to use.
As discussed at length in the related case, the modulator disclosed therein constitutes a fourth-order sigma-delta modulator that strikes a good balance between use of first-order modulators (which are less expensive than second-order modulators) and use of second-order modulators (which are easier to match than first-order modulators, but which are more expensive). The modulator disclosed in the related case is, however, somewhat complex, and it therefore requires use of a number of analog components. It is a shortcoming and deficiency of the prior art that there is not available a simpler, less expensive version of the Cabler modulator, which could be fruitfully used in many applications.